RF amplifiers, mixers, and filters are well known in the art of high frequency signal processing. An RF transmitter takes a baseband signal and modulates to a transmit frequency using an oscillator, mixer, and amplifiers. Typically, in an RF receiver, an amplifier increases the signal delivered by an antenna, and it is mixed to an intermediate frequency, or baseband frequency, and receives additional amplification. Prior art transmitters and receivers are typically constructed from high speed transistors and gain elements, and operate as analog elements, whereby a changing signal level on a single conductor carries all of the information required in the signal. For systems carrying analytic signals, a quadrature pair of signals is sufficient to fully describe the analytic signal.
FIG. 1 shows a prior art RF receiver comprising a baseband receiver 100, analog-digital conversion interface 120, and digital baseband receive processor 136, as well as a prior art transmitter comprising a digital baseband transmit processor 230, an analog-digital conversion interface 232, and a transmit modulator 200 coupled to a transmit antenna 202. These receiver and transmitter systems are well known for use in an 802.11 wireless system for receiving and transmitting ethernet packets. The baseband receiver 100 is shown as a dual conversion baseband receiver, and includes a receive antenna 102 for receiving incoming signals, an optional IF conversion stage 110, which includes a preamplifier 104 with an RF gain control 280 for control of preamplifier 104 gain. The preamplifier 104 drives a mixer 106, which also receives an input from a first local oscillator 108 such that the output of mixer 106 includes an image frequency at an intermediate frequency (IF), which is filtered by IF bandpass filter 238. The IF amplifier 240 receives this signal from the IF bandpass filter 238, and increases or decreases the signal level via IF gain control 242 before passing the signal on to the quadrature mixers 112 and 116, which are driven by quadrature oscillators 114 and 118. The quadrature mixing process generates quadrature outputs comprising an in-phase (I) and quadrature (Q) signal, which are the quadrature signal outputs of baseband receiver 100. The IF amplifier 240, or any subsequent stage which does signal processing after the variable gain control has been performed, generates a Receive Signal Strength Indicator (RSSI) status output 244, which is an analog signal related to signal strength after final amplification. This signal may be used by the digital baseband receive processor 136 to formulate the RF gain control 280 and IF gain control 242, which are analog signals after conversion by digital to analog converters (DAC) 134 and 132, respectively. Analog-digital converter interface 120 provides a conversion between the analog signal processing functions found in the baseband receiver 100 and the digital baseband receive processor 136. Analog quadrature baseband signals from the quadrature mixers 112 and 116 are filtered by low pass filters 124 and 128 before being digitized by analog to digital converters (ADC) 126 and 130, respectively. The analog-digital converter interface 120 also converts the analog RSSI status signal 244 into digital output for the digital baseband receive processor 136 status input, which also generates digital control outputs for IF gain and RF gain, which are fed to digital to analog converters (DAC) 132 and 134, respectively. The digital baseband receive processor 136 is generally an entirely digital functional block, which receives digital values and generates digital values, and these values are converted to and from analog values by the analog-digital converter interface 120, as has been described. In addition to RF and IF gain control management in response to either the RSSI status input or actual values presented to the in-phase (I) and quadrature (Q) channel interfaces, typical functions performed by the digital baseband receive processor 136 include signal stream synchronization, symbol extraction, demodulation, packet framing, and packet buffer management of ethernet packets received across analog-digital converter interface 120.
In addition to the double conversion heterodyne receiver shown in baseband receiver 100 which includes IF conversion stage 110, it is possible to omit the IF conversion stage 110 to form a direct, or single conversion receiver. In this case, incoming signals from receive antenna 102 are applied directly to IF amplifier 240, which is now acting as a gain controlled RF amplifier, in place of preamplifier 104. The output of the gain controlled RF amplifier 240 is fed to quadrature mixers 112 and 116. These quadrature mixers 112 and 116 are also receiving signals from quadrature oscillators 114 and 118 at the incoming RF frequency, thereby achieving direct baseband conversion and delivering quadrature outputs to analog-digital converter interface 120, as before.
The digital baseband transmit processor 230 of FIG. 1 performs analogous operations for the transmission of signals. Digital baseband transmit processor 230 removes packets for transmission from a packet buffer which may be shared with digital baseband receive processor 136, and converts the packet into a modulated baseband stream of quadrature digital data, which is digitized by digital to analog converters (DAC) 218 and 220, and then filtered by low pass filters 222 and 224. The resulting quadrature data stream from low pass filters 222 and 224 is converted to a modulation frequency by mixers 210 and 214 which are both fed by transmit oscillator 212. The signals are summed 206 and a single modulation product at the desired range of frequencies is selected via bandpass filter 208 and fed to power amplifier 204 which drives the transmit antenna 202. The power amplifier 204 accepts a gain control input 234, and also produces an RF output level status 236. The RF output level status 236 is converted by an ADC 228 and read by the digital baseband transmit processor 230, which may respond with a different value of digital transmit (TX) gain, which is converted by DAC 226 to TX gain control input 234 and fed to RF power amplifier 204. As with the digital baseband receive processor 136, the digital baseband transmit processor 230 is a function implemented using entirely digital components which may be integrated into a single digital integrated circuit or field programmable gate array (FPGA).
The digital signal processing of FIG. 1 is well known to one skilled in the art, and may be found in the disclosure of other wireless systems such as that described in U.S. Pat. No. 6,563,858 by Fakatselis et al, or in the datasheet for Intersil ISL3873B, datasheet number FN8019.2.